Job Description
Among. The top 4 IT companies, in India ranked by market capitalization and revenue
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ASIC RTL Lead
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Bangalopre / Hyderabad / Kochi
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Mandatory Skill : (RTL Design, RTL Coding & Integration, RTL quality checks (Lint, CDC), IP, targeted for SOC, Static checks, Protocols - PCIe, DDR, Ethernet,I2C, UART, SPI)
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Senior ASIC Engineer (IP RTL design targeted for SOC, Static checks, some basic protocols)
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Expertise in SoC subsystem/IP design
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Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog
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In depth knowledge on RTL quality checks (Lint, CDC)
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Knowledge of synthesis and low power is a plus
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Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB)
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Valuable understanding of timing concepts
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Knowledge of one or more of the interface protocols
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a. PCIe
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b. DDR
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c. Ethernet
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d. I2C, UART, SPI
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Expertise in setting up and using tools like
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a. Spyglass Lint/CDC
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b. Synopsys DC
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c. Verdi/Xcellium
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Understanding of scripting languages like Make flow, Perl ,shell, python etc
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Understanding of processor architecture and/or ARM debug architecture is a plus
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Able to help and debug issues for multiple subsystems
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Able to create/review design documents for multiple subsystems
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Able to support physical design, verification, DFT and SW teams on design queries and reviews
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Skills
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SoC
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PCIe
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DDR
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Ethernet
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LPDDR
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Verilog
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SystemVerilog
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Xcellium
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CPU
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ARM
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RISC-V
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Contact
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Uday
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[email protected]
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Mulya Technologies
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"Mining the Knowledge Community"
📌 ASIC RTL Design Lead (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru