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- Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs
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- Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure
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- Handle regression testing and contribute to verification infrastructure development
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- Develop both directed and random verification tests
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- Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues
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- Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement
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- Collaborate with design, software and architecture teams to verify design under test
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Preferred Experience:
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- Proficient in IP-level FPGA and ASIC verification
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- Knowledge of PCIe, CXL or other IO protocol is preferred
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- Proficient in Verilog/SystemVerilog,
and scripting languages such as Perl or Python
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- Hands-on experience with SystemVerilog and UVM is mandatory
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- Experience in developing UVM-based verification testbenches, processes, and flows
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- Solid understanding of design flow, verification methodology, and general computational logic design and verification
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About Company
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ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.
📌 Verification Lead (Hyderabad)
🏢 ACL Digital
📍 Hyderabad
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