Job Type: Full time

Senior Engineer, Package Design – Bengaluru, KA- IndiaTop 100 Global Semiconductor MNC in the worldBangaloreDescriptionWe are a innovative enterprise that designs, develops, and delivers System-on-Chip products to customers worldwide. The company is focused on AR/VR, imaging, networking, storage, and other dynamic technologies that drive today’s leading-edge applications. We combine world-class expertise, experience, and an extensive IP portfolio to provide exceptional solutions and ensure a better quality of experience for customers. Founded in 2015, We are headquartered in Japan, and have offices in Japan, Asia, United States and Europe to lead its product development and sales activities.Senior Engineer, Package Design – Bengaluru, KA- IndiaResponsibilities:The Package substrate design focus on signal and power integrities analyses as well as routing analyses. You will be reporting to the Director of Package Design (USA) and working very closely with Package design team in our parent company’s headquarters in Japan and Marketing and Engineering teams located in our Milpitas office during the pre/post sales process.This position requires a broad knowledge of package technology and design. Successful candidates will have a deep understanding and experience in the following areas: high performance build-up substrates, flip chip assembly or 2.5D packaging. Knowledge and experience in extracting/simulating package designs for Signal and Power integrities using tools such as HFSS, and/or ADS tools.Education:Bachelor’s degree in Electrical Engineering,



or other semiconductor packaging related disciplineMS is preferredRequired Experience and Skills:8 to 10 years of experience in semiconductor packaging design, modeling, extraction, and simulationsRecord of success in cross-functional team environmentGood experience with Signal and power integrity tools for package level modeling/extraction/simulationAbility to work with Package Layout engineers.Strong presentation and communication skillsPreferred Experience and Skills:Hands-on package design; high-speed Signal integrity and Power integrity and package decoupling caps optimizations, combined package and PCB Signal integrity and Power integrity Characterizations, impedance verification, high frequency s-parameters extraction, Hspice model, package Hspice and RLC model extraction and designsHands-on high-speed package and PCB design for: high-speed Serdes 112 Gbps, PCIeX5 and 6, LPDDR4,5, Ethernet 25 GBps, power aware SI/PI analysis, up to 40 GHZ s-parameters extraction and verificationPackaging+PCB high-speed interconnections timing analyses, eye-diagram and jitter budgeting calculation following the LPDDR JEDEC spec,



or other highs-speed frequency domain s-parameters extraction following the base Spec of high-speed interconnectHands-on PCB design; SI, PI analyses, decoupling caps optimizations, SI and PI Characterization and extractions, impedance verification, s-parameters verifications with lab measurements, Hspice model, PCB RLC model extraction and designsPackaging routing analyst, trace impedance analyses and package layout bump to ball analysesPackage material characterization frequency dependent model; skin effects, smoothness, roughness, dielectric loss and dielectric constantPCB material characterization frequency dependent; routing degree of freedomTime domain analyses and jitter budgeting for PCIe2/3/4/5, Serdes 112 GBps, Ethernet 25 Gbps, LPDDR4/5X MIPI, high-speed frequency signalingTime domain analyses and budgeting model for LPDDR 3/4/5, LPDDRX 3/4/5/6Bathtub curve and BER analyses of high speed signalingDDR frequency and time domains model and jitter analyses and path findings to improve package and PCB layout and improve high-speed interconnectionsClk jitter analyses, routing, clk tree analysesSimulating multi-physics electro-thermal analysisCollateral packaging manufacturing and assembly rulesChip and package Reliability analysesDie+Pkg+pcb PDN model time and frequency, Impedance profile, AC droop, DC drop DC, etc.IR drop, and CPM (chip power model) die model using Redhawk and other tollsCore PI: simulation capability, tool/flow and past experience on measurement capability, lab tool set up.Contact:UdayMulya [email protected]‘Mining The Knowledge Community‘

📌 Senior Package Design Engineer (Karnataka)
🏢 Mulya Technologies
📍 Karnataka