Below is the JD for RTL engineers. We need to build robust RTL team.
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- Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV
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- Experience in Logic design/micro-architecture/RTL coding is a must.
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- Must have hands on experience with design and integration of complex multi clock domain blocks
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- Experience in Verilog/System-Verilog is a must.
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- Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architecture
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- Hands on experience in Multi Clock designs, Asynchronous interface is a must.
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- Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.
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- Work closely with the Design verification and validation teams for pre/post Silicon debug
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- Hands on experience in Low power design is preferable
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- Experience in Synthesis / Understanding of timing concepts for ASIC is must
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