Job Description
TITLE: RTL DESIGN ENGINEER(SMTS)
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LOCATION: GREATER BENGALURU AREA
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Company Description
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At Tsavorite Scalable Intelligence , we are pioneering the semiconductor industry’s first Omni Processing Unit (OPU)—a breakthrough composable architecture designed to power the next generation of real-time, multi-modal Agentic AI .
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Founded in 2023 by a veteran team from Intel, Nvidia, Qualcomm, and Apple , we are on a mission to eliminate the cost, power, and complexity bottlenecks of legacy GPU systems. Our technology delivers a 10x performance gain at 10% of energy consumption, scaling seamlessly from edge devices to exascale data centers.
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Why Engineers Join Us:
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- Architectural Innovation: Work on the MultiPlexus™ fabric , a revolutionary interconnect offering petabyte-scale bandwidth and ultra-low latency.
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- Full-Stack Impact: We are building everything from modular chiplets on Samsung’s SF4X platform to our Tsavorite AI Orchestration Stack (TAOS) , which provides zero-switching-cost compatibility for CUDA-optimized workflows.
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- Market Momentum: We emerged from stealth with over $100 million in pre-orders from Global 500 companies and sovereign cloud providers.
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Key Links to Include
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- Official Website: tsavoritesi.com
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- LinkedIn Page: Tsavorite Scalable Intelligence | LinkedIn
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- Recent News: Tsavorite Emerges with $100M in Orders & 10x Performance (Forbes)
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JOB DESCRIPTION:
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Job Title: Design Engineer (Front-End/RTL)
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Role Overview
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As a Design Engineer, you will be the bridge between high-level architecture and physical
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implementation. You will own the development of critical SoC subsystems/IPs, translating
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complex architectural requirements into productive, high-performance RTL. This role requires
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someone who thrives on solving complex design challenges and can maintain design integrity
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through the rigors of synthesis, timing, and verification.
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Key Responsibilities
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- Micro-architectural Definition: Translate high-level architectural requirements into
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robust, detailed micro-architectural specifications.
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- Design & Implementation: Develop high-quality, synthesizable RTL using Verilog and
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SystemVerilog, ensuring designs meet performance, power, and area (PPA) targets.
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- Strategic Analysis: Conduct deep-dive analyses of implementation options, weighing
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trade-offs between latency, throughput, and silicon real estate.
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- Full Front-End Flow: Drive the design through the ASIC front-end suite, including
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Synthesis, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC).
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- Timing Ownership: Take responsibility for timing closure to ensure the design meets
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frequency targets across all corners.
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- Cross-Functional Collaboration: Manage design iterations by working closely with the
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Verification team and the Physical Design team
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- Debugging: Root-cause complex issues across simulation, linting, CDC, and synthesis
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environments.
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Required Qualifications
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Education & Expertise
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- Degree: Bachelor’s or Master’s degree in EC/EE/CS or a related field.
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- Experience: 8-14+ years of proven experience in SoC or Subsystem-level design.
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- Good understanding of the AMBA protocols, specifically CHI, AXI, AHB, and APB.
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- Expert-level proficiency in Verilog/SystemVerilog and micro-architecture development.
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- Hands-on experience with CDC/RDC tools, Linting, and Logic Synthesis (e.g., Design compiler, Genus).
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- Strong proficiency in Static Timing Analysis (STA) and timing constraints
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- Good understanding of ARM architecture is desirable.
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- Strong communication skills to articulate complex technical trade-offs to stakeholders
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Uday
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[email protected]
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"Mining the Knowledge Community"
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📌 RTL Design Engineer-SMTS (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru