Job Description

Job Title :IP Verification Engineer – UVM verification

n

Exp Level:4+ yrs

n

Location:Bangalore/Hyderabad

n

Job Description:System Verilog based UVM Functional verification, Behavioral modelling of functional blocks. System level performance verification, traffic patterns, bandwidth & latency analysis. Expertise in AXI4 bus protocol. Experience in Network On Chip (NOC) protocol. Experience in multi-master, multi-slave AXI4 use-case configurations. Knowledge of DRAM memory controllers.

n

Develop and execute testbenches to validate the functionality and correctness of models, as well as participate in system-level testing and debugging.

n

Basic Job Deliverable:Setup verification setting and bring up simulations with various simulations such as VCS / Questa / Xcellium / Riviera

n

SV/UVM Functional verification

n

Expertise in Vivado for simulation debugs

n

Qualification:B.E/M.E/M.Tech

n

n

Interested can Share CV to [email protected]

📌 IP Verification Engineer (Bengaluru)
🏢 ACL Digital
📍 Bengaluru