FPGA Design Technical Leader- Ethernet,PCIe, System Verilog, Xilinx- 12+ Years

Your Impact
Design and implementation of FPGAs.
Participate in the architecture definition, implementation and verification phases.
Detailed design specification and test plan development.
Develop and implement block level RTL, perform synthesis and achieve timing closure.
Work with multi-functional teams (hardware, software, diagnostics and signal integrity groups).
Assist in complex subsystem level lab bring-up, integration, and unit test validation.
Contribution to the design process adoption with in the team.

Minimum Qualifications
Educational Background: Requires 12+ years of experience in FPGA designs with MTech/BTech in EE/EC domain.
Experienced in crafting with Xilinx, Altera and Microsemi FPGAs or Proficiency in HDL languages (Verilog, VHDL and System Verilog)
Hands on experience with FPGA vendor tools like Vivado,



Quartus and Libero
Hands-on experience with Ethernet based protocols, PCIe, AXI, memory controllers, OTN, I2C, SPI, UART etc. Familiarity with simulation flow like UVM and VMM will be an added advantage.
Basic knowledge on Unix system and script tool.
Promote continuous improvement in design methodologies and processes
Lead and mentor junior design engineers, offer technical guidance, and drive successful project execution
Facilitates/encourages knowledge sharing in the team (e.g., brownbags, demos, design sessions).

Preferred Qualifications
Knowledge on the signal integrity and system bring-up.
Valuable English written and verbal communications. Self-motivation, partnership and robust interpersonal skills are needed.

📌 Fpga Design Technical Leader Bengaluru (India)
🏢 Cisco
📍 India