We are looking for an experienced Senior Physical Design / STA Engineer with 5+ years of hands-on experience in advanced semiconductor technology nodes, preferably TSMC <5nm, to join our chip design team.

The ideal candidate will have strong expertise in Static Timing Analysis (STA) along with solid knowledge of physical implementation, timing closure, and signoff methodologies. Experience working with Synopsys and Cadence EDA tools is highly preferred.

Key Responsibilities

- Perform Static Timing Analysis (STA) for advanced-node ASIC/SoC designs.
- Drive timing closure across multiple PVT/MMMC corners and operating modes.
- Analyze and resolve setup, hold, recovery, removal, and clock-related timing violations.
- Work closely with RTL, Synthesis, Physical Design, CTS, and Signoff teams to achieve timing targets.
- Perform post-synthesis and post-route timing analysis.
- Develop and validate timing constraints including SDC, clocks, generated clocks, false paths, and multicycle paths.
- Analyze clock skew, latency, uncertainty, OCV/AOCV/POCV, and other advanced timing effects.
- Support optimization of timing, power, and area (PPA).
- Debug timing issues related to placement, routing, congestion, signal integrity, and library constraints.
- Perform timing ECOs and recommend appropriate design/implementation changes.
- Work on advanced-node challenges associated with TSMC <5nm technologies.
- Collaborate with Physical Design and Signoff teams for STA, SI, IR/EM, and final timing signoff.




- Support methodology development, automation, and flow improvements using Tcl/Python.

Required Skills
- 5+ years of relevant experience in ASIC Physical Design / STA.
- Strong hands-on experience in Static Timing Analysis and timing closure.
- Experience with advanced technology nodes, preferably TSMC 5nm/4nm/3nm or below.
- Strong knowledge of:
- SDC constraints
- MMMC analysis
- Setup/Hold analysis
- Clock Tree concepts
- OCV/AOCV/POCV
- SI/Crosstalk
- Timing ECOs
- Path-based and graph-based analysis
- MCMM timing closure
- Robust understanding of ASIC physical design flow from synthesis through signoff.
- Proficiency with Synopsys PrimeTime and/or Cadence Tempus.
- Experience with Synopsys ICC2/Design Compiler and/or Cadence Innovus/Genus is desirable.
- Good scripting skills in Tcl; Python/Perl is an added advantage.
- Strong debugging and problem-solving skills.

Preferred Qualifications
- Experience with TSMC advanced-node design flows (<5nm).
- Experience with high-performance CPU/GPU/AI/Networking/SoC designs.
- Exposure to high-speed interfaces such as PCIe, DDR, SerDes, Ethernet, or similar.
- Experience with low-power and high-frequency designs.
- Understanding of advanced-node library, variation, and parasitic modeling.
- Experience in full-chip timing signoff and tapeout activities.

Pay: ₹1,552,270.61 - ₹3,032,967.85 per year Work Location: Hybrid remote in Bengaluru, Karnataka

📌 Senior Physical Design Engineer (Bengaluru)
🏢 Chiplogic Technologies
📍 Bengaluru