We are hiring experienced ASIC Verification Engineers with robust hands‑on expertise in SystemVerilog, UVM, and IP/SOC verification. The role involves leading a small team, defining testbench architecture, developing UVM settings, and driving coverage closure. Experience with debug tools (IUS/VCS/Questa/Verdi), scripting (Python/Perl/Shell), and protocols like AXI, PCIe, DDR, USB, CXL, Ethernet, etc., is highly preferred. Knowledge of CPU-based verification, NoC, low‑power/GLS is a plus. Robust ownership and communication skills are essential.