TITLE: RTL DESIGN ENGINEER(SMTS) /n LOCATION: GREATER BENGALURU AREA /n /n Company Description /n At Tsavorite Scalable Intelligence , we are pioneering the semiconductor industry’s first Omni Processing Unit (OPU)—a breakthrough composable architecture designed to power the next generation of real-time, multi-modal Agentic AI . /n Founded in 2023 by a veteran team from Intel, Nvidia, Qualcomm, and Apple , we are on a mission to eliminate the cost, power, and complexity bottlenecks of legacy GPU systems. Our technology delivers a 10x performance gain at 10% of energy consumption, scaling seamlessly from edge devices to exascale data centers. /n Why Engineers Join Us: /n /n
- Architectural Innovation: Work on the MultiPlexus™ fabric , a revolutionary interconnect offering petabyte-scale bandwidth and ultra-low latency.
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- Full-Stack Impact: We are building everything from modular chiplets on Samsung’s SF4X platform to our Tsavorite AI Orchestration Stack (TAOS) , which provides zero-switching-cost compatibility for CUDA-optimized workflows.
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- Market Momentum: We emerged from stealth with over $100 million in pre-orders from Global 500 companies and sovereign cloud providers.
/n /n /n Key Links to Include /n /n
- Official Website: tsavoritesi.com
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- LinkedIn Page: Tsavorite Scalable Intelligence | LinkedIn
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- Recent News: Tsavorite Emerges with $100M in Orders & 10x Performance (Forbes)
/n /n /n /n : /n Job Title: Design Engineer (Front-End/RTL) /n Role Overview /n As a Design Engineer, you will be the bridge between high-level architecture and physical /n implementation. You will own the development of critical SoC subsystems/IPs, translating /n complex architectural requirements into efficient, high-performance RTL.
This role requires /n someone who thrives on solving complex design challenges and can maintain design integrity /n through the rigors of synthesis, timing, and verification. /n /n Key Responsibilities /n - Micro-architectural Definition: Translate high-level architectural requirements into /n robust, detailed micro-architectural specifications. /n - Design & Implementation: Develop high-quality, synthesizable RTL using Verilog and /n SystemVerilog, ensuring designs meet performance, power, and area (PPA) targets. /n - Strategic Analysis: Conduct deep-dive analyses of implementation options, weighing /n trade-offs between latency, throughput, and silicon real estate. /n - Full Front-End Flow: Drive the design through the ASIC front-end suite, including /n Synthesis, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC). /n - Timing Ownership: Take responsibility for timing closure to ensure the design meets /n frequency targets across all corners. /n - Cross-Functional Collaboration: Manage design iterations by working closely with the /n Verification team and the Physical Design team /n - Debugging: Root-cause complex issues across simulation, linting, CDC, and synthesis /n environments. /n /n Required Qualifications /n Education & Expertise /n - Degree: Bachelor’s or Master’s degree in EC/EE/CS or a related field. /n - Experience: 8-14+ years of proven experience in SoC or Subsystem-level design. /n - Good understanding of the AMBA protocols, specifically CHI, AXI, AHB, and APB. /n - Expert-level proficiency in Verilog/SystemVerilog and micro-architecture development. /n - Hands-on experience with CDC/RDC tools, Linting, and Logic Synthesis (e.g., Design compiler, Genus). /n - Strong proficiency in Static Timing Analysis (STA) and timing constraints /n - Good understanding of ARM architecture is desirable. /n - Solid communication skills to articulate complex technical trade-offs to stakeholders /n Uday /n
[email protected] /n /n "Mining the Knowledge Community" /n
📌 RTL Design Engineer-SMTS (Bengaluru)
🏢 Mulya Technologies
📍 Bengaluru