Design and Verification Engineer (Bengaluru)

Design and Verification Engineer (Bengaluru)

22 Aug
|
Leadic Design
|
Bengaluru

22 Aug

Leadic Design

Bengaluru

DV Engineer with robust SystemVerilog and UVM skills. Experience in testbench development, constrained-random testing, functional coverage, assertions, regression, and RTL debug.

📌 Design and Verification Engineer (Bengaluru)
🏢 Leadic Design
📍 Bengaluru

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