Job Description Experience: 4-10 years
n Location - Bangalore/Pune
n Responsibilities:
n · Complete DFT ownership of projects including:
n n Test architecture definition.
n Identifying and implementing RTL changes for DFT.
n Performing scan insertion, LEC checks, low power CLP checks.
n Developing timing constraints for test mode timing closure.
n Scan and ATPG for different fault models.
n Boundary scan, ACJTAG, IEEE 1500 implementation and verification.
n IEEE1687 (iJTAG) compliant ICL/PDL for functional manufacturing tests.
n Running zero delay and timing simulations and debugging on all the above aspects.
n Supporting post silicon bring up.
n Interacting with customers on DFT aspects and support Marketing & Pre-Sales team.
n Experience working on very high speed and low power designs
n
📌 Lead DFT design Engineer (Bengaluru)
🏢 Cadence System Design and Analysis
📍 Bengaluru
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