Position: Senior DV Engineer - UVM/SystemVerilog (BB810ST RM 4328)
Very valuable knowledge of UVM and SystemVerilog.
Some networking experience/exposure is welcome.
Job Category: Others
Job Type: Full Time
Job Location: Bangalore
Experience: 8-10 years
Notice period: 0-30 days
Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.
📌 Sr DV Engineer - UVM/SystemVerilog (Bengaluru)
🏢 Sourceright Technologies
📍 Bengaluru
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