Position: Senior Formal Verification Engineer

Location: Bangalore

Experience: 8+ years

Notice Period: 30 days Max / Immediate Joiners Preferred

Role Overview

We are looking for a highly experienced Senior Formal Verification Engineer to own formal verification and sign-off for complex, high-speed IP blocks and subsystems. The ideal candidate will have strong expertise in Formal Property Verification (FPV), SystemVerilog, UVM, and advanced verification methodologies, with hands-on experience in complex protocol IPs such as DDR, PCIe, and Ethernet.

The candidate will work closely with RTL Design, Architecture, and Verification teams to develop robust formal verification strategies, debug complex counterexamples, achieve proof convergence, and drive verification closure.

Key Responsibilities

- Own end-to-end Formal Property Verification (FPV) for complex IP and subsystem blocks, from verification planning and property development through proof convergence and formal sign-off.
- Develop, review, and maintain SystemVerilog Assertions (SVA) for protocol compliance, data integrity, corner cases, and functional requirements.
- Perform formal connectivity checking, X-propagation analysis, CDC/RDC-adjacent formal analysis, and register/CSR formal verification.
- Apply advanced formal techniques such as abstraction, case splitting, cut-points, assumptions, constraints, and complexity reduction to achieve proof convergence.
- Verify complex, high-speed protocol IPs including DDR, PCIe, and/or Ethernet.
- Develop and review assertion-based verification environments and Assertion IP (AIP)



where applicable.
- Complement formal verification with System Verilog/UVM simulation-based verification, including test bench architecture, VIP integration, functional coverage, and coverage closure.
- Analyze and debug formal counterexamples and collaborate with RTL Design and Architecture teams to identify and resolve design or specification issues.
- Drive verification closure and contribute to formal sign-off criteria for IP and subsystem releases.
- Mentor junior verification engineers and promote formal verification methodologies, best practices, and reusable verification components.
- Contribute to improving formal verification flows, methodologies, automation, and overall team productivity.

Required Skills & Experience

- 8+ years of experience in semiconductor/ASIC/SoC verification with substantial hands-on ownership of Formal Verification.
- Strong practical expertise in Formal Property Verification (FPV) methodologies.
- Hands-on experience with industry-standard formal tools such as:
- Cadence JasperGold
- Synopsys VC Formal
- Solid proficiency in SystemVerilog and SystemVerilog Assertions (SVA).




- Strong UVM expertise and experience with simulation-based verification environments.
- Proven experience verifying complex, high-speed protocol IPs such as:
- DDR
- PCIe
- Ethernet
- Strong understanding of AMBA protocols, including AXI, AHB, and APB.
- Experience with formal connectivity and architectural verification.
- Strong debugging and problem-solving skills, particularly in analyzing formal counterexamples and convergence issues.
- Ability to work closely with RTL Design, Architecture, and Verification teams.
- Experience in verification planning, coverage analysis, and sign-off methodologies.

Good to Have

- Experience with high-speed SerDes or PHY-layer verification.
- Exposure to low-power verification and UPF-based formal verification flows.
- Experience developing reusable Assertion IP (AIP).
- Experience with CDC/RDC verification and related formal methodologies.
- Experience leading formal verification activities or owning verification sign-off for major IPs/subsystems.
- Prior experience mentoring junior engineers or leading a verification team.
- Experience working on complex SoC-level verification environments.

Key Skills / Keywords SystemVerilog | UVM | SVA | Formal Verification | FPV | DDR | PCIe | Ethernet | Cadence JasperGold | Synopsys VC Formal | AMBA | AXI | AHB | APB | Assertion IP | Connectivity Verification | X-Propagation | CDC/RDC | SoC Verification | ASIC Verification

Pay: ₹300,000.00 - ₹2,084,517.80 per month

Education

- Bachelor's (Preferred)

Work Location: In person

📌 Senior Formal Verification Engineer (Bengaluru)
🏢 FB Veritas TechP
📍 Bengaluru