Senior RTL Design Engineer /n Location: Hyderabad /n Experience: 3–6 Years /n Role Overview /n We are looking for a Senior RTL Design Engineer with robust hands-on expertise in Ethernet-based SoC/IP design, RTL development, and design quality checks. /n Key Responsibilities /n /n
Develop and integrate synthesizable RTL for complex SoC/IP designs.

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Solid hands-on experience with Ethernet protocols/IP and high-speed networking designs.

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Translate microarchitecture specifications into efficient RTL.

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Perform Lint, CDC/RDC and RTL quality checks using SpyGlass.

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Debug and resolve RTL, CDC, lint and functional issues.

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Collaborate with Architecture, DV, STA and Physical Design teams.

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Drive RTL optimization for PPA, timing, area and power.

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Solid Verilog/SystemVerilog RTL design experience.

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Solid microarchitecture understanding and ability to work from specifications.

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Strong Ethernet knowledge — MAC/PCS/PHY, 10G/25G/100G/400G exposure preferred.

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Hands-on experience with SpyGlass Lint & CDC.

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Strong understanding of CDC, reset architecture, clocking and RTL coding practices.

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Experience with synthesis, timing and PPA optimization.

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Strong debugging and problem-solving skills.

/n /n Ideal Candidate: A hands-on RTL engineer with strong Ethernet + Microarchitecture + Lint/CDC + SpyGlass expertise and experience delivering production-quality SoC/IP designs.

📌 Senior Rtl Design Engineer Hyderabad (India)
🏢 leadsoc technologies
📍 India