Job Description

STA Design Engineer

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We need experienced Static Timing Analysis engineers to design and integrate an ARM/RISCV-based SoCs in cutting edge technology and with complex functionality.

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Skills:

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Overall 3+ years industry experience in Backend (Physical Design) STA at SoC level.
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Hands-on experience with Timing constraints authoring, managing complex clocking, reset, and design hierarchy.
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Proven experience in minimum 2 Tape-out sign offs.
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Knowledge of IP and SoC design flows and methodologies
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Ability to work with local and remote teams (Architecture, RTL, DFT, and Physical Design)
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Proficient in EDA tools used (e.g. Cadence/Mentor/Synopsys)
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Working knowledge of Unix, Linux and SKILL, Shell/Python Script ability.
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Quick learner with excellent interpersonal, verbal/written communications, problem solving and decision-making skills
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Traits:

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Adaptable, Adaptable, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a robust sense of urgency.
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Solutions orientation; Quality driven; Execution minded
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📌 Static Timing Analysis Sta Engineer Hyderabad
🏢 Sevya Multimedia
📍 Hyderabad