Job Description

Hi All,

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Job Location: Bangalore

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Notice Period: 15 days to 30 Days

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Minimum: 5+ Years

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1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.

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Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus.

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Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus.

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Experience with hardware architecture exploration, performance modelling will be a big plus.

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Prior experience in Machine learning/Artificial Intelligence domain and/or DRAM Memory controllers is a plus.

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6.Must have experience in Lint and CDC.

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7.Must have RTL Design worked on PCIe/CXL

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Thanks,

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K Himabindu

📌 Senior Rtl Design Engineer Bengaluru
🏢 ACL Digital
📍 Bengaluru