Senior Memory Design EngineerExperience - (4–8 Years)Location:HyderabadAbout the RoleJoin a high-performance silicon engineering team developing next-generationSRAM and memory IPfor advanced SoCs. You will drive memory architecture, circuit design, characterization, and silicon optimization to deliver high-speed, low-power, and robust memory solutions across leading-edge process technologies.Key ResponsibilitiesDesign and optimizeSRAM and memorycircuits for performance, power, area, and yield.Develop memory building blocks includingbitcells, sense amplifiers, write drivers, row/column decoders, precharge circuits, redundancy, and peripheral logic .Perform transistor-level design, simulation, and verification acrossPVT corners, Monte Carlo, noise, and reliabilityanalyses.Drive post-layout verification (PEX) and collaborate with layout teams for optimal matching and manufacturability.Support silicon bring-up, characterization, failure analysis, and yield improvement.Work closely with architecture, physical design, DFT,



and product engineering teams throughout the memory development lifecycle.Required QualificationsB.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, or related discipline.4–8 yearsof hands-on experience inSRAM or memory circuit design .Robust understanding ofCMOS device physics, transistor-level design, memory architecture, stability, and reliability .Proficiency withCadence Virtuoso, Spectre, ADE XL/Assembler, and extraction tools such asCalibre xRC/StarRC .Experience withpost-layout simulation, PEX, LVS/DRC, EM/IR, and silicon correlation.Scripting experience inPython, SKILL, Perl, or TCLis a plus.Preferred ExperienceExperience with advanced process nodes ( FinFET technologies ).Exposure tohigh-performance CPU, GPU, AI Accelerator, Networking, or Data Center SoCs .Knowledge of low-voltage memory design, yield optimization, and low-power techniques.

📌 Senior Memory Design Engineer (Maharashtra)
🏢 Leadsoc Technologies
📍 Maharashtra