Lead &review; RTL design, verification planning (UVM)physical design handoffs across multi-engineer teams
Own end-to-end chip/SoC architecture block partitioning process node/technology selection
Drive EDA tool-flow selection &setup; digital synthesis
Required Candidate profile
7–10 yrs hands on VLSI design Exp spanning at least two of RTL/digital design, analog/mixed-signal design, physical design DV/UVM verification
Robust in CMOS device physics digital logic SPICE-level
📌 VLSI Design Engineer - Architect Role (Chennai)
🏢 Trion consultancy Services
📍 Chennai
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