Role Overview

We are seeking a highly experienced Senior Staff Verification Engineer to lead the design verification of next-generation high-speed interconnect IPs and SoCs. The ideal candidate will bring deep expertise in PCIe, CXL, Ethernet, UCIe protocols, and advanced SystemVerilog, UVM methodologies, C and SV skills, driving verification strategy, execution, and innovation across complex projects.

What You’ll Do

- Verification Strategy: Define and implement scalable verification plans for PCIe, CXL, and Ethernet subsystems.
- UVM Testbench Development: Architect layered UVM agents, environments, and reusable components for protocol verification.
- Protocol Expertise: Apply in-depth knowledge of PCIe Gen5/Gen6, CXL 3.x, and Ethernet (200G/400G), UCIe PHY and Adaptor layer standards to ensure compliance and robustness.
- Coverage & Metrics: Drive functional coverage closure, assertion-based verification, and metric-driven sign-off.
- Debug & Analysis: Lead root-cause analysis of complex issues across simulation, emulation, and silicon bring-up.
- Collaboration: Partner with design, architecture, and validation teams to deliver high-quality IP and SoC verification.
- Mentorship: Guide junior engineers,



fostering best practices in verification methodology and protocol expertise.

What We’re Looking For

- Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in Design Verification, with strong exposure to complex SoC/IP verification
- Proven experience in defining and deploying verification architectures for high-speed protocols
- Strong expertise in SystemVerilog, UVM, coverage-driven verification, and SVA
- Deep hands-on experience with PCIe Gen5/Gen6, CXL 3.x, Ethernet 200G/400G or similar protocols
- Experience with UCIe PHY/Adapter layer verification is highly desirable
- Strong understanding of SoC architecture, high-speed interfaces, and IP integration
- Excellent debugging, problem-solving, technical leadership, and mentoring skills

Positive to Have

- Experience with AI/ML applications in verification workflows
- Exposure to emulation, prototyping, or hybrid verification platforms
- Familiarity with performance verification and power-aware verification
- Knowledge of industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe)
- Experience building verification frameworks reused across multiple tape-outs

📌 Senior Staff Engineer - Design Verification (Bengaluru)
🏢 tylsemi
📍 Bengaluru