Design Verification Engineer (3 - 9 Years)

Location: Pune | Notice Period: 45-60 days (Serving notice period only)

Responsibilities & Requirements

- Core Verification: Execute full-cycle ASIC/SoC and IP-level verification from initial planning through tape-out.
- Testbench Development: Build and maintain UVM/SystemVerilog testbenches, sequences, and coverage-driven test suites.
- Protocol & Bus Verification: Verification experience with AMBA bus architectures; familiarity with PCIe, Ethernet, or USB preferred.
- Coverage Closure: Implement directed and random test cases to achieve targeted functional and code coverage goals.
- HW/FW & Low-Power: Exposure to low-power strategies (UPF, boot sequences) and HW/FW interactions is a robust plus.
- Cross-Team Collaboration: Work closely with design, firmware, and architecture teams to integrate and verify complex FPGA features.
- Qualifications: BS/MS in EE/CS; 3+ years of hands-on IP/SoC Design Verification experience.

📌 Design and Verification Engineer (Pune)
🏢 ACL Digital
📍 Pune