As a Senior Manager in Silicon Design Validation, You lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products. Your role provides strategic oversight and technical direction across the full post-silicon lifecycle, from first silicon arrival to production release.

Key Leadership Areas:

- Technology Enablement Learning Culture Fostering a learning environment where engineers gain hands-on experience with FPGA architectures and foundational IP blocks such as SERDES (PMA/PCS), DDR memory (DDR4, LPDDR4, DDR5), DPHY, PLLs, DSPs, MIPI, Fabric, and I/O subsystems.

- Validation/Characterization Strategy Execution Overseeing the validation and characterization of analog, digital, and mixed-signal IPs, ensuring robust coverage from initial silicon bring-up through production qualification.

- Planning Infrastructure Development Guiding the development of validation plans, including bench hardware and software requirements, and ensure the team has the necessary tools and infrastructure to execute effectively.

- RTL Development for Test Enablement Supervising the creation of custom RTL test logic to support targeted validation and characterization efforts, enabling deeper insight into IP behavior.

- Silicon Bring-Up Debug Leadership Driving the bring-up of new silicon products, driving validation and debug activities to assess IP functionality and performance. This includes characterizing datasheet parameters, performing statistical analysis of measured data, and overseeing datasheet preparation.





- Cross-Functional Collaboration Acting as the central liaison between design, verification, manufacturing, test, quality, and marketing/application teams, ensuring alignment and smooth transition from silicon arrival to product release.

- Customer Support Issue Resolution Providing leadership in resolving post-release customer issues, coordinating with internal teams to ensure timely and effective solutions.

You Have

- 15+ years of experience in silicon validation, including 3 5 years in a leadership role.

- Master or Bachelor s degree in Electrical Engineering with a robust passion for engineering and management in silicon design validation.

- Proven track record in managing complex validation projects and leading cross-functional teams.

- Deep expertise in high-speed SerDes interface characterization and protocol compliance testing (e.g., PCIe, Ethernet, SDI, CoaXpress, JESD204, MIPI D-PHY, CSI/DSI-2, USB, DisplayPort, HDMI).

- Strong background in high-speed board design, signal integrity evaluation, and debug.

- Proficient in Verilog/VHDL and FPGA design implementation using industry-standard tools.

- Skilled in test automation development using Python and Perl.

- Solid understanding of statistical analysis and tools such as JMP and R.

- Hands-on experience with bench equipment including BERT, VNA, oscilloscopes, and protocol analyzers.

Disclaimer : This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Silicon Design Validation, Senior Manager (Pune)
🏢 Lattice Semiconductor (india)
📍 Pune