Project Role : Functional Verification Engineer
Project Role Description : Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level. Create constrained-random, directed, and coverage-driven tests using languages like SystemVerilog and UVM. Collaborate with design and architecture teams to identify corner cases and ensure complete functional coverage before tape-out.
Must have skills : SoC Verification
Valuable to have skills : NA
Minimum 5 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
As a Functional Verification Engineer, a typical day involves designing and implementing comprehensive testbenches to validate the functional accuracy of digital designs at both block and system levels. The role requires creating various types of tests, including constrained-random, directed, and coverage-driven, to thoroughly assess the design's behavior.
Collaboration with design and architecture teams is essential to uncover edge cases and guarantee exhaustive functional coverage prior to tape-out. This position demands a proactive approach to problem-solving and continuous communication across multiple teams to ensure the highest quality of verification outcomes.
Roles & Responsibilities:
DDR Protocol & Standards Knowledge
- Deep understanding of DDR4 (JEDEC JESD79-4) and DDR5 (JESD79-5) specifications
- Knowledge of DDR5 RCD (Registering Clock Driver), SPD Hub, and on-die ECC
- Familiarity with signal integrity concepts: eye diagrams, jitter, crosstalk, and impedance
- Understanding of DDR training algorithms: read/write levelling, ZQ calibration, ODT tuning
- Experience with LPDDR4/5 desirable
Verification Methodologies & Simulation
- Proficient in UVM (Universal Verification Methodology) for DDR PHY/Controller verification
- Experience writing SystemVerilog testbenches and functional coverage models
- Familiarity with formal verification methods and assertion-based ve