Job ID 2026-17741 Date posted Aug. 11, 2026 Location Bengaluru, India Category Design Engineering
We are seeking a highly skilled and technically proficient Engineer with experience in ASIC front-end methodologies across IP and SoC design domains. The ideal candidate will bring over 5+ years of VLSI experience, having successfully handled and deployed sophisticated automation flows, design checks and collaborated effectively to deliver cutting-edge solutions in the semiconductor domain. The role includes working with global design teams and internal collaborators to deploy IP/SoC design checks, integration methodologies and improve them continuously.
Responsibilities:
- Define the deployment of sophisticated front-end methodologies for ASIC design, including SoC Integration, LEC, CDC/RDC, SDC, linting processes for ASIC project.
- Apply automation in design check flows to improve the operating efficiencies.
- Collaborate closely with other design engineers in resolving all the design checks violations and sign-off the design check reports
- Collaborate closely with worldwide team on design methodology, define and evaluate the flows. Actively involve in defining the improvements in the methodology.
- Represent the company in technical conferences, working groups, and internal award forums.
Required Skills and Experience:
- 5+ years of experience in VLSI ASIC design and methodology development and deployment.
- Demonstrated experience in executing and driving design check activities for complex SoC projects.
- Expertise in EDA tools such as SpyGlass, VC RDC, LEC, Design Compilers, and formal verification tools.
- Proficiency in scripting and automation using Python, Perl, TCL.
- Strong understanding of Verilog/System Verilog and front-end design verification techniques (CDC, RDC, Lint, FV, Synthesis).
"Nice to Have" Skills and Experience :
- Experience in leveraging AI-driven techniques to optimize and automate workflows within EDA environments.
- SDC and Timing Constr