We are looking for an experienced Design Verification (DV) Design Lead with strong expertise in PCIe SystemC IP / Subsystem Verification to drive high-quality pre-silicon verification and ensure robust, bug-free silicon.

The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, functional and formal verification, verification planning, coverage closure, regression automation, and verification sign-off. Experience with mixed-signal IP, RNM/Verilog-A, C/MATLAB modelling, Specman e, and functional safety (ISO 26262) will be highly valued.

Key Responsibilities

- Lead and execute pre-silicon verification activities for PCIe SystemC IPs and subsystems.
- Develop and maintain high-quality SystemVerilog/UVM-based verification environments.
- Create detailed verification plans, define verification strategies, and drive execution.
- Develop and execute functional and formal verification methodologies.
- Drive functional coverage, code coverage, and coverage closure activities.
- Develop, debug, and maintain test cases suitable for regression.
- Run verification regressions and support the setup and automation of continuous regression environments.
- Analyze failures, perform root-cause analysis, and provide debug support to achieve verification sign-off.
- Prepare verification progress reports, KPI reports, and verification sign-off documentation.
- Work closely with cross-functional teams including design, architecture, modelling, and validation teams.
- Support verification setting qualification and ensure compliance with defined quality KPIs.




- Contribute to regression automation using Jenkins and scripting languages.
- Support Certitude closure and other formal/functional verification closure activities.
- Work effectively with international and multicultural technical teams.

Required Skills & Experience

- 7–20 years of experience in semiconductor design verification.
- Strong hands-on experience in SystemVerilog and UVM.
- Proven experience in constraint-random functional verification.
- Experience with formal verification methodologies.
- Strong understanding of verification planning, testbench development, regression, debugging, and coverage closure.
- Experience in developing and qualifying verification environments.
- Hands-on experience with PCIe IP / subsystem verification is highly preferred.
- Experience with SystemC and IP/subsystem-level verification.
- Knowledge of Specman e is preferred; candidates willing to learn Specman e may also be considered.
- Experience with mixed-signal IP verification using RNM / Verilog-A models is an advantage.
- Experience in C modelling for digital signal blocks is desirable.
- Experience with MATLAB modelling will be an added advantage.
- Knowledge of regression and coverage analysis tools.




- Experience with Jenkins-based regression automation.
- Knowledge of scripting languages such as Python and Perl.
- Knowledge of functional safety and ISO 26262.
- Hands-on experience with verification tools such as Xcelium and Vmanager Enterprise Edition.
- Working knowledge of VHDL is desirable.
- Strong analytical, debugging, and problem-solving skills.
- Excellent English communication and interpersonal skills.

Key Deliverables

- Regression-ready and well-qualified verification test cases.
- Qualified SystemVerilog/UVM and Specman e verification environments.
- Verification plans, execution reports, and coverage closure reports.
- Verification sign-off reports meeting defined KPIs and coverage targets.
- Regular progress and KPI status reports.
- Effective debug support to achieve IP verification sign-off.
- Automated regression infrastructure and scripts using Jenkins.
- Successful Certitude and verification closure.

Tools & Technologies

SystemVerilog | UVM | SystemC | Specman e | Xcelium | Vmanager Enterprise Edition | VHDL | Python | Perl | Jenkins | Verilog-A | RNM | C Modelling | MATLAB | Certitude

Why Join This Opportunity

- Work on advanced PCIe IP and subsystem verification projects.
- Opportunity to work on complex semiconductor verification challenges.
- Collaborate with international and cross-functional engineering teams.
- Contribute to high-quality pre-silicon verification and silicon sign-off.
- Work with industry-standard verification methodologies and tools.

📌 Design Verification Design Lead – PCIe / SystemVerilog / UVM (Bengaluru)
🏢 Anlage Infotech India Private
📍 Bengaluru