Job Description
We’re Hiring – DFT Qualified‘s | 18+ Years Experience
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nGreetings from Eximietas Design
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nWe are looking for experienced Design for Test (DFT) professionals to join our growing VLSI team. If you are passionate about advanced silicon testing and SoC design, this is a great opportunity to work on complex IP, Subsystem, and SoC level projects.
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nLocations:
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- India:n
n Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam.
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nUSA Eligibility:
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- USA: San Jose (Bay Area) / Austinn
- U.S. Permanent Residents (Green Card holders) onlyn
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nExperience: 18+ Years
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nCompany: Eximietas Design
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nRole Overview
nYou will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, subsystem, and SoC designs.
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nCore Responsibilities
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- Own the complete DFT implementation flow from RTL to pattern sign-offn
- Define and implement scan architectures including EDT and OCCn
- Perform block-level ATPG, DRC analysis, and coverage optimizationn
- Execute pattern simulations (timing and non-timing)n
- Handle SoC-level integration and pattern retargetingn
- Integrate and debug MBIST, IJTAG, and Boundary Scan (JTAG)n
- Debug DFT simulations and netlist-related issuesn
- Collaborate closely with design, verification, and physical design teamsn
- Drive DFT sign-off activities and project deliverablesn
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nTechnical Requirements
nMust-Have Skills
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- Strong expertise in netlist handling and ATPG simulationsn
- Experience with block-level and SoC-level pattern retargetingn
- Understanding of ICL and PDL standardsn
- Hands-on experience with DFT tool suites such as:n
- Siemens Tessentn
- Synopsys TestMAX / TetraMAXn
- Cadence Modusn
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nPreferred Skills
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- Experience with Streaming Scan Network (SSN)n
- Knowledge of Analog & Mixed-Signal DFT methodologiesn
- Exposure to SpyGlass for DFT lintingn
- Experience in RTL-level DFT insertionn
- Strong scrip