Design and Verification Engineer (Hyderabad)

Design and Verification Engineer (Hyderabad)

10 Sep
|
Leadic Design
|
Hyderabad

10 Sep

Leadic Design

Hyderabad

Hiring PCIe & GLS Verification Engineers with 4+ years of experience in SystemVerilog/UVM. Experience in PCIe Gen5, GLS, RTL verification, assertions, coverage, debugging, and protocol verification preferred.

📌 Design and Verification Engineer (Hyderabad)
🏢 Leadic Design
📍 Hyderabad

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