Job DescriptionHiring: Staff Engineer - STA
NLocation: Hyderabad / Bangalore
NExperience: 10+ Years
NNotice Period: Immediate to 30 Days Preferred
NRole Overview
nWe are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in timing sign-off for complex SoC designs. The candidate should have hands-on experience in timing closure, constraints development, and working closely with PD and RTL teams to achieve design closure.
NKey Responsibilities
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- Perform block and full-chip Static Timing Analysis for complex SoC designs N
- Develop and validate timing constraints (SDC) N
- Drive timing closure across different corners and modes N
- Analyze and debug setup/hold violations N
- Work closely with Physical Design, RTL, and Architecture teams N
- Support ECO implementation for timing fixes N
- Handle timing sign-off for tape-out N
- Perform clock tree and timing path analysis N

nMandatory Skills
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- Solid expertise in Static Timing Analysis (STA) N
- Hands-on experience with Synopsys PrimeTime N
- Strong understanding oftiming constraints (SDC) N
- Experience in timing closure and sign-off N
- Understanding of clocking architecture and CDC concepts N
- Exposure to advanced technology nodes N
- Good understanding of Physical Design flow N

nGood to Have
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- Experience with CPU/GPUor high-performance SoC designs N
- Knowledge of Low Power (UPF/CPF) N
- Exposure to Synthesis and PD flow N
- Experience in ECO and sign-off flows N

nRequired Experience
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- 10+ years of experience in STA / Timing Analysis N
- Strong debugging and problem-solving skills N
- Ability to work independently and drive timing closure N

nInterested candidates can share resumes with [email protected]

📌 Hiring: Staff Engineer (Karnataka)
🏢 BITSILICA
📍 Karnataka