Job DescriptionTechnical Lead - Design Verification
nExperience: 8+ Years
nLocation: Bengaluru
nWe are seeking a highly skilled and experienced Senior Design Verification Engineer to join our SoC/ASIC verification team in Bangalore. The ideal candidate will have a deep understanding of the verification lifecycle, from test planning to coverage closure, and be able to independently drive complex verification tasks for IP, subsystem, or full-chip level designs.
nKey Responsibilities:
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Develop and execute test plans for IP/subsystem/full-chip level verification.n
Build and maintain constrained-random and directed testbenches using SystemVerilog and UVM.n
Drive functional coverage closure and ensure high-quality tape-outs.n
Collaborate with RTL designers, architecture, and software teams to understand design features and define test scenarios.n
Participate in code reviews, debug RTL/testbench issues, and file bug reports.n
Use industry-standard tools like VCS, QuestaSim, Verdi, Synopsys, Cadence, or Mentor toolchains.n




Mentor junior team members and lead small verification teams or projects when required.n
Support post-silicon validation teams and participate in bring-up/debug if necessary.n

nRequired Skills and Qualifications:
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B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or related field.n
8+ years of experience in ASIC/SoC design verification.n
Robust expertise in SystemVerilog, UVM, and object-oriented programming.n
Proven track record in building and maintaining verification settings from scratch.n
Experience in assertion-based verification, coverage analysis, and debug tools.n
Solid understanding of digital design concepts, SoC architecture, and protocols like AMBA (AXI, AHB), PCIe, USB, or DDR.n
Hands-on experience with simulation tools, waveform viewers, and version control systems (Git, Perforce, etc.).n
Excellent problem-solving, communication, and team collaboration skills.n

📌 Staff Engineer Vasanthanagar
🏢 ACL Digital
📍 Vasanthanagar