We are looking for an experienced SoC/IP Design Verification Engineer with strong hands-on expertise in SystemVerilog, UVM and C-based verification . The role will focus on SoC verification, Test Controller and MBIST verification, functional vector generation, vector bring-up and silicon/wafer characterization .
The ideal candidate should have strong knowledge of DFT/Test Controller architecture , excellent debugging and constrained-random verification skills, and experience working closely with Architecture, Design and ATE/Tester teams .
Key Responsibilities
- Create and execute SoC verification plans and develop C/SystemVerilog/UVM-based verification tests .
- Develop a strong understanding of SoC architecture and Test Controller architecture .
- Develop SystemVerilog/UVM testcases for:
- Test Controller verification
- MBIST verification
- Functional vector generation
- Develop SV/UVM monitors and verification components to measure performance and improve the verification environment.
- Collaborate with Architecture, Design and ATE/Tester teams to identify ASIC test-vector and functional-pattern requirements.
- Develop and automate verification environment development flows using scripting and automation methodologies.
- Drive verification automation and contribute to improving team productivity and regression efficiency.
- Participate in vector bring-up activities and support ATE/Tester teams during functional characterization .
- Debug functional vectors and silicon/wafer issues and work with cross-functional teams to drive issues to closure.
- Apply AI-assisted verification tools and methodologies to improve verification productivity and efficiency.
Required Qualifications
- Bachelor's or Master's degree in Engineering, preferably Electronics/Electrical/Computer Engineering or related discipline.
- 6+ years of hands-on SoC/IP Design Verification experience .
- Strong proficiency in SystemVerilog and UVM .
- Experience developing verification environments and testcases using C/SystemVerilog/UVM .
- Good understanding of SoC architecture and Test Controller / DFT architecture .
- Hands-on experience with Test Controller and MBIST verification .
- Proven experience in ATE / functional characterization vector enablement on silicon or wafers.
- Strong experience in vector bring-up and silicon/wafer debug .
- Strong understanding of:
- Constrained-random verification
- Functional verification
- Debugging
- Verification planning
- Proficiency in scripting/automation using Python, Perl and/or TCL .
- Positive understanding of industry-standard interfaces such as PCIe, LPDDR and ONFI/NAND is desirable.
- Experience working with AI tools and AI-assisted verification methodologies .
- Strong problem-solving, communication and cross-functional collaboration skills.
- Positive, proactive and ownership-driven approach.
Good to Have
- Experience working directly with ATE/Tester teams .
- Experience in ASIC test-vector development and functional pattern generation.
- Experience with silicon validation / wafer-level characterization .
- Experience automating verification flows and improving verification infrastructure.
- Exposure to memory technologies and interfaces such as LPDDR and ONFI/NAND .