:

Design and develop FPGA systems for real-time signal processing, precision instrumentation and control. Develop Verilog/VHDL RTL, implement DSP, interface high-speed ADC/DAC, perform timing closure, hardware debugging and system integration.

Total Experience : 5 - 10 years

Requirements :

- 5+ years FPGA/RTL development.
- Strong Verilog/VHDL/SystemVerilog, Xilinx, preferably Zynq/Zynq UltraScale+.
- Experience in DSP, ADC/DAC, timing closure, CDC, simulation, hardware bring-up and debugging.

Required Skills and Experience :

- 5+ years of handson FPGA/RTL development experience.
- Proficiency in Verilog, VHDL, and SystemVerilog.
- Solid experience with Xilinx devices, preferably Zynq or Zynq UltraScale+ families.
- Demonstrated expertise in DSP implementation, highspeed ADC/DAC interfacing, and timing closure.
- Solid background in CDC techniques, simulation tools, and hardware debugging.

Preferred Skills :

- Experience with highlevel synthesis (HLS) or MATLAB/Simulink codesign.
- Familiarity with PCIe, Ethernet, or other highspeed communication protocols.
- Knowledge of embedded Linux on Zynq platforms.

📌 Senior FPGA Systems Engineer (India)
🏢 Smarthyre
📍 India