Design and Verification Engineer (Bengaluru)

Design and Verification Engineer (Bengaluru)

11 Sep
|
Silicon Patterns
|
Bengaluru

11 Sep

Silicon Patterns

Bengaluru

Roles and Responsibilities :

- Design and develop testbenches using SystemVerilog/UVM for complex digital circuits.

- Collaborate with cross-functional teams to identify requirements and create verification plans.

- Develop high-quality test cases, scenarios, and scripts to ensure thorough coverage of the design's functionality.

- Analyze results, debug issues, and provide recommendations for improvement.

- Must have PCIe gen6

Job Requirements :

- 5-10 years of experience in PCIe protocol.

- Solid understanding of SV (SystemVerilog) programming language and UVM (Universal Verification Methodology).

- Experience working on large-scale projects involving multiple stakeholders from various domains.

📌 Design and Verification Engineer (Bengaluru)
🏢 Silicon Patterns
📍 Bengaluru

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