Job Description#Urgent_Opening_for_Canvendor Nn#Hiring: PD EMIR (5+ Years Experience) | Chennai | Immediate to 15 Days NnJobTitle: PD EMIR NYears of Experience: 5+ Years NLocation: Bengaluru/Hyderabad NWork Mode: WFO NnRequired Experience: Nn 5+ years of overall VLSI/Physical Design experience is preferred. N 3+ years of hands-on experience in PDN and EMIR closure for digital ASIC designs. N Strong expertise with industry-standard EMIR analysis and sign-off methodologies. N Excellent debugging, analytical, and cross-functional collaboration skills. NnKey Responsibilities: Nn Own SoC-level IR Drop, Signal EM, and Power EM sign-off for complex digital ASIC designs. N Drive EMIR closure by identifying root causes of power integrity and electromigration violations. N Debug challenging EMIR issues and provide optimized, practical solutions to achieve sign-off. N Collaborate closely with the Physical Design (PD) team to drive effective IR/EM closure across the chip. N Analyze power delivery networks (PDN) and recommend improvements for robust power integrity. N Ensure timely closure of EMIR sign-off while meeting performance, power, and reliability targets. NnnIf interested kindly share your updated CV to [email protected]