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- Worked on 7nm/5nm/Future sub-micron Technologies.
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- Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus.
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- Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality.
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- Familiar with pre-STA timing analysis using Primetime or Tempus.
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- Familiar with low power check using Conformal Low Power or VCLP tool.
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- Experience in verifying constraints quality and completeness.
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- Understanding of UPF & Low power concepts.
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- Familiar with functional ECO flow and implementation.
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- Familiar with DFT Insertion and debugging basic DFT issues.
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- Co-work with RTL, DFT and PD engineers to meet PPA targets.
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- Well versed with TCL/Perl/Shell script.
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- Self-starter and highly motivated.
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- Robust debugging, initiative and analysis/problem solving skills.
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- Minimum 3+ years of experience in Synthesis and Physical Synthesis
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