We are seeking an experienced ASIC Design Engineer with deep expertise in high-speed interface protocols to join our silicon engineering team. The ideal candidate will have a solid background in digital design, micro-architecture, and implementation of high-speed protocols such as PCIe, Ethernet, USB, or SerDes-based interfaces, and will contribute across the full ASIC development lifecycle.
- Architect and design high-performance digital blocks for ASIC/SoC targeting high-speed protocols (e.g., PCIe Gen4/5, 100G/400G Ethernet, USB3/4).
- Develop RTL using Verilog/SystemVerilog with a focus on performance, power, and area optimization.
- Define micro-architecture and interface specifications for protocol IPs.
- Collaborate with verification teams to develop test plans, debug failures, and ensure coverage closure.
- Work closely with physical design teams for synthesis, timing closure, and floorplanning support.
- Analyze and debug silicon bring-up issues related to high-speed interfaces.
- Integrate third-party IPs (SerDes, PHYs) and ensure proper functionality and interoperability.
- Participate in design reviews and ensure adherence to design methodologies and best practices.