Hiring Location: Bangalore

nExperience: 8-12 Years

nWe are seeking a Staff DFT Engineer who can own and drive the complete DFT strategy for complex SoCs from architecture through production silicon. This role requires deep hands-on expertise, robust technical judgment, and the ability to lead and mentor junior engineers while collaborating cross-functionally with design, PD, validation, and manufacturing teams.

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nThe ideal candidate operates independently, makes architecture-level decisions, and is accountable for test quality, coverage, and silicon readiness .

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nResponsibilities:

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nDFT Architecture & Planning

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- Own DFT architecture definition at chip and subsystem level
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- Define scan, compression, LBIST, MBIST, boundary scan, and test access strategies
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- Drive testability requirements early in the RTL design phase
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- Balance coverage, test time, power, area, and schedule tradeoffs
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nDFT Implementation (End-to-End Ownership)

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- Lead and execute:
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- Scan insertion, stitching, and DRC closure
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- ATPG (stuck-at, transition, path delay)
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- Test compression and pattern optimization
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- Own DFT signoff including coverage, IR drop, power, and timing impacts
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- Debug and resolve DFT issues across RTL, synthesis, P&R;, and gate-level stages
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nATPG & Test Quality

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- Generate, analyze, and optimize ATPG patterns
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- Achieve high fault coverage with minimal pattern count
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- Review and sign off on:
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- Fault coverage reports
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- Pattern volume and test time
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- Diagnose coverage holes and drive design or methodology fixes
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nSilicon Bring-Up & Production Support

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- Support first silicon bring-up, failure analysis, and yield ramp
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- Debug scan, BIST, and tester-related failures
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- Collaborate with ATE and manufacturing teams to improve yield and test robustness
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- Drive ECOs for DFT-related silicon issues
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nTechnical Leadership & Mentorship

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- Act as DFT technical lead for one or more chips
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- Guide and review work of junior and senior DFT engineers
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- Define best practices, checklists, and reusable DFT methodologies
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- Provide technical direction and design reviews
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nCross-Functional Collaboration

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- Work closely with:
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- RTL designers
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- Physical design (PD)
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- Functional verification
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- Product engineering and manufacturing
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- Communicate DFT requirements and risks clearly to stakeholders
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nPreferred/Nice-to-Have Experience:

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- Experience with high-volume production test, ATE bring-up, and test cost optimization.
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- Exposure to safety-critical applications (automotive, industrial) and standards (e.g., ISO 26262) from a test/reliability standpoint.
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- Experience with on-chip debug, trace, and design-for-debug features.
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- Scripting skills in Python/Tcl/Perl for DFT automation, log analysis, and flow integration.
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- Prior experience mentoring or leading small DFT teams or task forces.
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nQualifications and Experience:

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- Proven experience in leading DFT teams through end-to-end SoC execution, from architecture to silicon bring-up.
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- Demonstrated expertise in developing DFT architecture from scratch for complex SoC designs.
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- Strong team management and leadership experience with a track record of mentoring and growing engineering talent.
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- Bachelor's or Master’s degree in Electrical/Electronics Engineering or a closely related field.
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- 7+ years of hands-on experience in DFT methodologies and industry-standard test techniques.
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- Deep knowledge and hands-on experience with:
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📌 DFT Engineer (Bengaluru)
🏢 Capgemini Engineering
📍 Bengaluru