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Experience: 7+ yrs

Location: bangalore

Job Type: Full-time

We are looking for an experienced DFT Engineer with robust hands-on expertise in Design for Testability (DFT) for complex ASIC and SoC designs. The role focuses on developing and implementing DFT architectures, scan insertion, scan-chain implementation, MBIST, ATPG, test-pattern generation, and DFT verification.

The ideal candidate will have a robust understanding of semiconductor test methodologies and the ability to own DFT activities across the design lifecycle, from architecture and implementation through pattern generation, verification, coverage analysis, and sign-off.

Requirements

KEY RESPONSIBILITIES
- Develop and implement DFT architectures for complex ASIC and SoC designs.
- Define and implement scan architecture, scan insertion, and scan-chain structures.
- Develop, debug, and validate ATPG patterns for stuck-at, transition, and other fault models.




- Implement and verify MBIST solutions for embedded memories.
- Analyse and improve test coverage, fault simulation results, and pattern quality.
- Perform DFT rule checks and identify and resolve DFT-related design violations.
- Integrate DFT logic into RTL and netlist flows while ensuring compatibility with synthesis and physical implementation.
- Debug scan-chain, ATPG, MBIST, test-coverage, and pattern-simulation issues.
- Support scan-chain diagnosis and DFT-related design debugging.
- Collaborate with RTL, Design Verification, Physical Design, STA, and Silicon Validation teams.
- Support DFT verification, ATPG pattern simulation, and silicon bring-up activities.
- Review DFT requirements and contribute to overall test strategy and methodology development.
- Analyse fault coverage and identify opportunities to improve test quality and efficiency.
- Support DFT implementation through synthesis, physical design, timing, and sign-off stages.

📌 DFT Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru