About This Job
ACL Digital
Location: Hyderabad, Telangana, India
Work Mode: On-site
Industry: Engineering Services,Semiconductor Manufacturing
RTL & FPGA Design Engineer
Experience : 4-6 years
Location : Hyderabad
Core Skills: RTL Digital Design (Verilog/VHDL), Vivado toolchain (Design creation to Bitstream generation), and timing/IO constraints.
Architecture & Interfaces: Strong grasp of AXI/AHB/CHI/ACE5 buses, peripherals (USB, Ethernet), and Video IPs (ISP/Encoder/Decoder).
Debugging & Tools: Industry-standard front-end waveform debugging, ILA, Unix workplace, and scripting (Tcl/Python/Perl).
Bonus: Hands-on experience with pre-silicon platforms and automated verification flows.
Interested candidates, please send your resume to
[email protected]!
📌 RTL - FPGA Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad