- Lead full-chip Physical Verification (PV) sign-off activities.
- Own and drive DRC, LVS, ERC, and related physical verification checks.
- Lead PV closure from block level through full-chip sign-off.
- Analyze and debug complex DRC/LVS/ERC violations and drive them to closure.
- Work closely with Physical Design teams to resolve physical verification issues.
- Coordinate with Foundry/PDK teams for rule interpretation and verification issues.
- Review and debug verification results from large, complex SoC designs.
- Drive PV schedules, milestones, issue tracking, and sign-off readiness.
- Develop and improve PV methodologies, flows, and automation.
- Support tapeout/sign-off activities and ensure quality of final verification results.
- Mentor and provide technical guidance to PV engineers.




- Collaborate with Physical Design, Custom Layout, CAD, STA, DFT, and other teams.
- Participate in methodology reviews and improve verification turnaround time.

Experience (years) : 10+ years

Education Qualification

BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

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📌 PV Lead (Bengaluru)
🏢 Mirafra
📍 Bengaluru