Title: Lead Synthesis & STA Engineer

Location: Bangalore

Experience: 8+ Years

We are looking for an experienced Lead Synthesis & STA Engineer with robust expertise in RTL synthesis, full-chip Static Timing Analysis (STA), and Cadence EDA tools.

Key Responsibilities

- Lead RTL synthesis, timing analysis, and optimization for complex SoC designs.
- Perform full-chip STA, timing closure, and setup/hold violation analysis.
- Drive timing, power, and area (PPA) optimization.
- Work on SDC constraints development, validation, and timing exceptions.
- Collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.
- Lead design reviews, debug critical paths, and drive closure activities.

Must-Have Skills

- 8+ years of experience in RTL Synthesis and Static Timing Analysis.
- Strong hands-on experience with Cadence Genus and Tempus .
- Expertise in full-chip STA, timing constraints, and timing closure.
- Strong knowledge of SDC, setup/hold analysis, and timing optimization.
- Experience with PPA optimization and advanced SoC design flows.

📌 Lead Synthesis & STA Engineer (Bengaluru)
🏢 LanceSoft
📍 Bengaluru