We’re looking for someone with strong hands-on experience in ATPG, scan, and DFT flows, with the ability to independently handle DFT tasks and debug complex issues.

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nMust Have:

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- 3+ years of SoC/ASIC Digital Design with DFT experience
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- Robust hands-on ATPG experience
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- ATPG coverage analysis and fault coverage improvement
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- ATPG pattern verification using no-timing and SDF-annotated simulations
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- Debugging simulation miscompares and root-cause analysis
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- Knowledge of scan chain insertion and DFT insertion flows
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- Good understanding of MBIST
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- Strong problem-solving and systematic debugging skills
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nGood to Have:

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- DFT architecture experience
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- Compression scan, LBIST, and advanced scan technologies
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- JTAG 1149.1/1149.6, IEEE 1500, IEEE 1687
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- Hands-on experience with Cadence DFT tools/flows
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- Synthesis and Verilog testbench debugging
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- Timing analysis and equivalency checks
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📌 DFT Engineer (Tamil Nadu)
🏢 LanceSoft
📍 Tamil Nadu