Experience: 5+ Years (Minimum 2+ Years in CPU/Processor RTL Design)

Required Qualifications & Skills

- Education: B.Tech / M.Tech in Electronics, VLSI, Microelectronics, or Computer Engineering.
- Experience: 5+ total years in ASIC/SoC RTL Design, with at least 2+ years dedicated to CPU core or processor subsystem RTL design (RISC-V, ARM, x86, or proprietary cores).
- Hardware Description Languages: Proficient in SystemVerilog, Verilog, and VHDL.
- CPU Microarchitecture Knowledge: Understanding of computer organization instruction execution pipelines, hazard handling, branch prediction, L1/L2 caches, memory management units (MMU), and interrupts.
- Bus Protocols: Hands-on experience with AMBA protocols (AXI, AHB, APB, ACE, CHI).
- Front-End Tools: Hands-on experience with Synopsys SpyGlass (Lint/CDC), VCS, Design Compiler (DC), or Cadence Genus/Xcelium.
- Scripting: Python, Perl, TCL, or Bash for automation. Preferred Qualifications
- Experience with low-power design techniques (Clock Gating, UPF/CPF intent definition).
- Exposure to FPGA prototyping or post-silicon bring-up and debug.
- Familiarity with assembly programming (RISC-V/ARM) for basic diagnostic bring-up tests.

📌 CPU RTL Engineer (Bengaluru)
🏢 G.t.d Technologies
📍 Bengaluru