Company:

LeadSoc Technologies Location:

Bangalore Experience:

2+ Years Notice Period:

0–30 Days preferred Job Summary LeadSoc Technologies is looking for a

Memory Layout Engineer

with 2+ years of relevant experience in custom/analog layout, preferably with hands-on experience in memory layout and advanced semiconductor technologies. Key Responsibilities Develop and implement

custom layouts for memory circuits

such as SRAM and other memory macros. Perform transistor-level layout of

bit cells, peripheral circuits, sense amplifiers, decoders, write drivers, and related blocks . Work closely with circuit designers to understand schematics and layout requirements. Ensure layout quality with respect to

DRC, LVS, ERC and PEX

requirements. Perform layout optimization for

area, matching, parasitics, power, and performance . Handle





full-custom layout

using industry-standard EDA tools. Debug and resolve physical verification issues. Support

ECOs, design iterations, and post-layout verification . Collaborate with design, verification, and physical verification teams to meet project schedules.

Preferred Experience working on

memory macros, bit cells, or memory peripheral circuits . Exposure to

FinFET / advanced-node technologies . Candidates with

relevant hands-on Memory Layout experience

will be preferred over profiles with only general/analog layout experience. Interested candidates can share their updated resume with: [email protected]

📌 Memory Layout Enginer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru