/n
Worked on 7nm/5nm/Future sub-micron Technologies.
/n
Hands on experience in Physical Synthesis with Multi corner & Multi-mode, Low Power, Performance and Area Goal using Fusion Compiler or Genus.
/n
Hands on experience in Logic equivalence check and low power check debugging and clean up using Conformal LEC or Formality.
/n
Familiar with pre-STA timing analysis using Primetime or Tempus.
/n
Familiar with low power check using Conformal Low Power or VCLP tool.
/n
Experience in verifying constraints quality and completeness.
/n
Understanding of UPF & Low power concepts.
/n
Familiar with functional ECO flow and implementation.
/n
Familiar with DFT Insertion and debugging basic DFT issues.
/n
Co-work with RTL, DFT and PD engineers to meet PPA targets.
/n
Well versed with TCL/Perl/Shell script.
/n
Self-starter and highly motivated.
/n
Robust debugging, initiative and analysis/problem solving skills.
/n
Minimum 3+ years of experience in Synthesis and Physical Synthesis
/n