Lead STA & Synthesis Engineer

nLocation: Bengaluru

nExperience: 8–12 Years

nRole Overview

nWe are looking for a Lead STA & Synthesis Engineer with solid hands-on expertise in Static Timing Analysis, RTL Synthesis, timing closure, and implementation flows for complex SoC designs.

nKey Responsibilities

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Own RTL-to-gate synthesis and timing analysis for complex SoC/IP designs.
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Drive STA, timing constraints, and timing closure across MCMM/MMC scenarios.
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Develop, validate, and debug SDC constraints, clocks, exceptions, and timing paths.
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Perform setup/hold analysis, critical path analysis, and timing optimization.
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Work closely with RTL, Physical Design, DFT, and implementation teams to resolve timing issues.
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Analyze and optimize area, power, and performance (PPA) during synthesis.
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Drive ECOs and timing fixes through implementation and signoff.
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Debug synthesis/STA issues including unconstrained paths, false paths, clock interactions,



and constraint violations.
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Develop scripts and automation using Tcl/Python/Perl to improve flow efficiency.
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nCore Technical Requirements

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8–12 years of experience in STA, synthesis, or front-end implementation.
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Robust expertise in Synopsys Design Compiler / Fusion Compiler or equivalent synthesis tools.
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Strong hands-on experience with Synopsys PrimeTime or equivalent STA tools.
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Deep understanding of SDC, MCMM/MMC, setup/hold, clocking, OCV/AOCV/POCV, and timing exceptions.
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Experience with RTL synthesis, timing optimization, and ECO flows.
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Robust understanding of ASIC/SoC implementation and signoff methodologies.
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Proficiency in Tcl/Python/Perl scripting.
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Experience with advanced technology nodes and complex SoC designs is preferred.
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📌 Lead Sta & Synthesis Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru