At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

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This role requires close interaction with multiple cross functional teams across geographies to align on project receivables/deliverables.
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Mentoring junior engineers and driving innovation/automation.
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BE/B.Tech/M.E/M.Tech with 3+ years of relevant work experience and robust understanding of DFT concepts and valuable communication skills.
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Robust hands-on experience using industry standard EDA Tools.
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Experience with logic simulators from one or more EDA vendors.
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Experience on industry standard ATPG tools like Cadence Modus.
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Experience with RTL lint tools like Jasper.
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Experience in scan insertion,



coverage analysis and debugging skills on faults coverage enhancement is required.
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Programming in Perl/Tcl/Python or other scripting languages is a plus.
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Experience in post silicon validation, ATE debug and support is desired.
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Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop.
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Positive understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis are plus.
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Participate in driving current DFT methodology and solutions to improve quality, reliability and in-system test and debug capability.
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📌 Lead Dft Design Engineer Bengaluru
🏢 Cadence System Design and Analysis
📍 Bengaluru