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Hands-on experience in developing/understanding building block schematics, memory schematics, running circuit simulation with spice simulators, DC analysis, transient analysis.
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Experience in deciphering circuit behavior from schematics
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Familiarity with circuit characterization, timing libraries - files and formats, timing arcs
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Experience in Verilog MOS switch level models and netlist simulation with zero delay, unit delay, and path delay simulations.
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Hands-on experience with latch based designs and their timing requirements.
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Debugging Gate level simulation failures and root causing the failures to actual circuits.
Accomplish what-if analysis by doing the change and making sure the fix can solve the issue.
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Robust communication skills, with the ability to convey complex technical concepts to other design peers in verbal and written form.
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Gate level simulation, spice correlation, Debug failures and provide fixes at gate or transistor level - as applicable.
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nRequired Qualifications
nEducation Qualification : BE/B.Tech or ME/M.TECH with 5+ Years of experience
nMinimum 6+ yrs of hands-on experience in circuit design, verification
nLocation- Hyderabad
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nInterested candidates can share resume to
📌 Senior Analog Design Engineer Hyderabad
🏢 ThunderSoft India Private
📍 Hyderabad
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