We are looking for a skilled STA Engineer with solid expertise in subsystem or full‑chip level STA closure. This role requires hands‑on experience with advanced tools and methodologies to drive timing sign‑off at scale.
Key Requirements
- Proven experience in subsystem/full‑chip STA closure
- Strong skills in constraint hacks and validation
- Hands‑on exposure to tools: PT, PrimeClosure, Tempus, Tweaker
- Experience in flat level and subsystem ECO rolling
- Focus on post‑layout STA (Note: Pre‑layout STA or PnR + STA profiles are not required)
What We’re Looking For
- Candidates with deep expertise in VLSI/ASIC STA
- Ability to work on complex timing challenges in advanced technology nodes
- Strong problem‑solving and debugging skills
📌 STA Engineer (Bengaluru)
🏢 QTIMinds Private
📍 Bengaluru
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