Experience to join our Silicon Engineering team. In this role, you will lead end-to-end DFT strategies—including Scan compression, MBIST, IJTAG, and ATPG pattern generation—for high-performance, sub-10nm So Cs. Candidates must have expertise in top-tier EDA tools (Tessent, Synopsys, or Cadence) and a notice period of 0–30 days.
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