Analog layout_4-8 years_Bangalore_Immediate joiner (Bengaluru)

Analog layout_4-8 years_Bangalore_Immediate joiner (Bengaluru)

13 Oct
|
AIonSi
|
Bengaluru

13 Oct

AIonSi

Bengaluru

Company Description AIonSi is a semiconductor solutions startup delivering VLSI design and verification, automotive functional safety, and artificial intelligence solutions to semiconductor clients worldwide. Led by a team of seven industry experts, the company focuses on end-to-end ownership of complex SoC designs, from initial concept through final implementation. AIonSi positions itself as a one-stop platform, emphasizing best-in-class service and uncompromising quality. The organization offers deep expertise in IP and SoC design, integration, verification, gate-level simulation (GLS), and physical design, providing a comprehensive environment for engineering professionals to grow their skills.
Role Description This is a full-time, in office Analog Layout Engineer role based in Bengaluru South. The individual in this position will be responsible for creating and optimizing analog and mixed-signal layout designs, ensuring compliance with design rules, performance targets, and reliability requirements. Daily tasks include collaborating with circuit design engineers, performing layout vs.



schematic (LVS) and design rule checks (DRC), and supporting tape-out activities. The role involves working on complex IP and SoC-level blocks, participating in design reviews, and contributing to layout methodologies and best practices. The engineer will also assist in debug and optimization during verification and sign-off, adhering to project schedules and quality standards.
Qualifications
• Strong hands-on experience in analog and mixed-signal layout design, including transistor-level layout, matching techniques, and parasitic-aware design.
• Proficiency with industry-standard layout and verification tools (such as Cadence Virtuoso, Calibre or equivalent) and familiarity with DRC, LVS, and parasitic extraction flows.
• Solid understanding of CMOS processes, physical design constraints, and layout considerations for precision analog, RF, or high-speed interfaces.
• Ability to coll

📌 Analog layout_4-8 years_Bangalore_Immediate joiner (Bengaluru)
🏢 AIonSi
📍 Bengaluru

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